DD&T Digital Design & Technology Gesellschaft für Hard- und  Software Entwicklung mbH  Electrical Engineering & IT Design Services

During recent years, the computer aided design of FPGAs and ASICs has made great progress in terms of design time and reliability. Still, the design flow may become very complex or require a great deal of interface adjustments, depending on the technology (and design kit) used.
DD&T  provides solutions for every aspect of a design flow, ranging from simple shell scripts to automate the design flow or filtering tool outputs to complete EDIF- or VHDL-parsers with task specific backends, correction of flaws or errors in the netlist output of tools.

Examples for tools developed by DD&T :

• A tool for inserting scan registers in a structural netlist (flat or hierarchical), with features to generate appropriate testpatterns for the resulting scan path.
• A tool for analyzing structural netlists that provides an intuitive visualization of selected regions of a netlist to help the designer understand synthesis results better, and also provides automated checks for a set of rules to which the netlist should comply to.
• A GDSII-parser and Viewer to analyze and convert layout data.

• Vendor independent consulting for the selection of EDA tools suited for your tasks
• Extension of EDA tools on hand, i.e. interfacing between tools of different vendors.
• Development of EDA tools
• VHDL/Verilog code reviews with respect to synthesis and technology to ensure quality results.
• In-depth training for all state ot the art EDA tools (Mentor Graphics, Model Technology and Exemplar, Synopsys, Cadence, Synplicity, ...)
• Basic design flow training:

- Design entry (VHDL IEEE 1076/1164, Verilog, Design for Testability)
- Technology specific synthesis (for example XILINX, Altera, Actel and ASIC technologies)
- Design verification (pre-synthesis simulation, backannotation, post-synthesis timing simulation, timing analysis)
- Foundry interaction (netlist verification, testpattern generation, pinout, ...)