The HEPI ASIC's task is to filter scientific data delivered by 2 detectors of the INTEGRAL satellite before transmission to earth. The HEPI  ASIC has a low speed (64 Kbit) serial link for communication setup-, status- and command data with the Data Processing Unit (DPE). The HEPI ASIC contains 2 fast UARTs (4 MHz) for collecting the two independent data streams from the detectors, 2 SRAM memory interfaces, 2 independent 16 bit FIFO controllers and five complex arithmetic units for processing scientific data. Data processed by the HEPI ASIC is sent to the DPE via 2 fast serial links (5 MHz), controlled by the HEPI ASIC.

The HEPI development started with an FPGA (XILINX XC4085 XLA) based prototype. Additionally, the HEPI environment was modeled in detail in a VHDL Testbench, implementing all communication protocols. After successfully testing the prototype, the FPGA design was transferred to a radiation hardened ASIC technology, optimized and verified. The ASIC was then manufactured by TEMIC/MHS.