DD&T Digital Design & Technology Gesellschaft für Hard- und  Software Entwicklung mbH  Electrical Engineering & IT Design Services

DD&T offers you support for all aspects of your ASIC project, ranging from specification, project organization and prototype development to
design implementation and interaction with the chip manufacturer. DD&T is independent of a specific manufacturer and therefore able to select the technology with the best price/performance ratio.

DD&T has, during many time critical and complex projects, proven the feasibility of the project with successful prototyping, and by utilizing
protocol oriented HDL-testbenches, efficiently retargeted the design to an ASIC technology.
Ever since the the availability of useable synthesis tools and silicon compilers, DD&T has developed using VHDL or Verilog, exploiting the possibilities to shorten the design cycle with the deployment of sophisticated HDL-testbenches. The testbenches developed by DD&T not only serve the purpose of functional verification but also
 

• model the timing behaviour of the system as close to reality as possible and are therefore useful for forward- and backannotation simulations.
• log system events with a variety probing mechanisms
• allow basic code coverage analysis
• support test infrastructure for device testing of ASICs (generating scan pattern, analyzing scan-out results, eventually setup and control of a JTAG controller)
• allow comparing simulations and testpattern generation for fault simulations

Mitsubishi Electric Research Lab (ITA/MERL): Architecture specification of the vg500 ASIC for real-time volume rendering (Used as rendering engine on the VolumePro PCI card from  RTViz )
	IAAT Tübingen/ESA: Development of the SECOM ASIC for the satellites ABRIXAS and XMM, and the HEPI ASIC for the INTEGRAL satellite.
EU ESPRIT project: Blending ASIC for acceleration and enhancement of image quality  for 3D-Graphics.