Some of the tools developed by DD&T for internal use proved to be so helpful that we decided to offer them as an addition to standard design flows (for Unix/Linux or Windows NT/Windows 98 platforms).

The Structural Netlist Viewer allows the visual exploration of hierarchical EDIF Netlists as well as structural VHDL/Verilog netlists. In contrast to the usual, cluttered schematics of synthesis results, the user choses an area of interest, for which the local connectivity is displayed. In addition to visual exploration, a set of automatic, mostly technology independent, checks allows to verify conformance to design rules.
 

The following tests are supported
- Fanout/Load Violations  - Shorts to Power/Ground  - Unconnected Input Gate Ports / Primary IO-Pins  - Delay Lines / Uncontrolled Pulse  - Spikes on Primary Outputs  - Combinatorial Loops  - Non-Controlled Reset and States  - Non-Controlled High Impedance  - Shift Register Constructs  - Wired Or Constructs
The Structural Netlist Viewer is especially useful for finding and analysing synthesis problems. It can be used for FPGA and ASIC technologies.	Incl. strokes controlled  schematic viewer!

Key-Features:
- Conversion to several layout formats  - Integrated viewer (controlled by strokes)  - Several options for visualization      (for example layer- or structure-specific)  - Easy integration of custom layout manipulations